1. Field of the Invention
The invention relates generally to a circuit configuration and method of manufacture of a transient voltage suppressor (TVS). More particularly, this invention relates to an improved circuit configuration and method of manufacturing a transient voltage suppressor (TVS) with improved clamping voltages.
2. Description of the Relevant Art
The transient voltage suppressors (TVS) are commonly applied for protecting integrated circuits from damages due to the inadvertent occurrence of an over voltage imposed onto the integrated circuit. An integrated circuit is designed to operate over a normal range of voltages. However, in situations such as electrostatic discharge (ESD), electrical fast transients and lightning, an unexpected and an uncontrollable high voltage may accidentally strike onto the circuit. The TVS devices are required to serve the protection functions to circumvent the damages that are likely to occur to the integrated circuits when such over voltage conditions occur. As increasing number of devices are implemented with the integrated circuits that are vulnerable to over voltage damages, demands for TVS protection are also increased. Exemplary applications of TVS can be found in the USB power and data line protection, digital video interface, high speed Ethernet, notebook computers, monitors and flat panel displays.
FIG. 1A-1 shows a typical commercially available two-channel TVS array 10. There are a pair of steering diode, i.e., diodes 15-H and 15-L, and 20-H and 20-L respectively for each of the two input/output (I/Os) terminals I/O-1 and I/O-2. Furthermore, there is a Zener diode, i.e., main diode 30, with a larger size to function as an avalanche diode from the high voltage terminal, i.e., terminal Vcc, to the ground voltage terminal, i.e., terminal Gnd. At a time when a positive voltage strikes on one of the I/O pads, the high side diodes 15-H and 20-H provide a forward bias and are clamped by the large Vcc-Gnd diodes, e.g., the Zener diode 30. The steering diodes 15-H and 15-L and 20-H and 20-L are designed with a small size to reduce the I/O capacitance and thereby reducing the insertion loss in high-speed lines such as fast Ethernet applications. FIG. 1A-2 shows the reverse current IR versus reverse blocking voltage VR characteristics between the Vcc and the ground voltage of the TVS array 10 shown in FIG. 1A-1. The reverse current IR as that shown in the diagram of FIG. 1A-2 represents a reverse current conducted through the Zener diode, i.e., between Vcc and GND. Here it is assumed that the reverse breakdown voltage (BV) of each steering diode is higher than the reverse BV of the Zener diode. But note that at high currents when the Vcc to Gnd pad voltage is equal or higher than the summation of the reverse BV of the steering diodes then the current would also flow through all the two series steering diode paths. Since the Zener diode has higher resistance per unit area compared with bipolar junction transistor (BJT) or semiconductor controlled rectifier (SCR) and BJT this is actually a disadvantage at higher currents because the steering diodes also have to be rugged in reverse conduction. In the case of the SCR+BJT the Zener clamp voltage is lower at higher currents and hence the steering diodes paths will not conduct. The breakdown voltage of the Vcc-Gnd diode 30 and the steering diodes 15 and 20 should be greater than the operating voltage (VRWM) so that these diodes only turn-on during the voltage transients. The problem with the Vcc-Gnd clamp diodes is that typically these diodes are very resistive in reverse blocking mode and require large area to reduce resistance. As shown in FIG. 1A-2, the high resistance leads to the increase of BV at high current. This is not desirable as high BV not only causes the break down of steering diodes as described above but also causes damage to the circuit the TVS device intends to protect. The requirement to have large diode size thus limits further miniaturization of a device when such TVS circuit is implemented.
One common method used in the integrated circuits to circumvent this drawback is to use a Zener triggered NPN as the clamp device as that shown in FIG. 1B-1. The TVS circuit 50 shown in FIG. 1B-1 comprises a NPN bipolar transistor 55 connected in parallel to a Zener diode 60 to function as a Zener triggered NPN bipolar TVS device. FIG. 1B-2 shows a current-voltage (IV) diagram for the Zener triggered NPN diode device. FIG. 1B-2 illustrates that when the collector voltage of the NPN 55 reaches the breakdown voltage BV of the Zener diode 60, the NPN bipolar turns-on and snaps back to a lower voltage called the BVceo or holding voltage of the NPN bipolar transistor 55 where BVceo stands for collector to emitter breakdown voltage with base left open. However, in a device that implements a TVS circuit, the snap-back phenomenon is not desirable. The snap-back creates a sudden drop of the reverse voltage that often causes the circuit oscillations due to negative resistance, or can even drop into the operating voltage of the device the TVS circuit is supposed to protect.
In order to resolve the snap-back difficulties, a patent application Ser. No. 12/454,333, of which this application is a Continuation-in-Part, was previously submitted on May 15, 2009 by a common inventor of this application. The disclosures made in that Application are hereby incorporated by reference in this patent application. The TVS circuits as described in the patent application Ser. No. 12/454,333 are implemented with a semiconductor controlled rectified (SCR) circuit to reduce the voltage-drop in a reverse-blocking voltage snap-back when a reverse current transmitted over a Zener diode triggers and turns on an NPN bipolar transistor. The TVS circuits disclosed in the patent application Ser. No. 12/454,333 resolve the difficulties caused by increasing break down voltage due to TVS device resistance and drastic voltage drop due to a snapback that commonly occurs in the conventional TVS circuit. Another aspect of application Ser. No. 12/454,333 was to provide an improved device design and manufacturing method to provide an improved TVS circuit. Furthermore, the TVS invention in the patent application Ser. No. 12/454,333 disclosed a new TVS for integration into mainstream complementary metal oxide semiconductor (CMOS) or Bipolar-CMOS (Bi-CMOS) technology allowing a configuration of single chip TVS protected ICs thus reduced the costs for providing the protected ICs on the electronic devices.
FIG. 1C illustrates the improved snapback profile of the SCR TVS circuit compared to the prior art. However, the reduced snapback shown in patent application Ser. No. 12/454,333 is achieved through elaborate layout configurations and difficult optimizations which can be difficult to design and implement, therefore there is still a need to further improve and simplify the clamping voltage of the TVS device.
Therefore, a need still exists in the fields of circuit design and device manufactures for providing a new and improved circuit configuration and manufacturing method to resolve the above-discussed difficulties. Specifically, a need still exists to provide new and improved TVS circuits that occupy small areas, eliminate or reduce the snapback voltage variations and furthermore that the TVS circuit can further improve the clamp voltage.